Astera Labs achieved a 3.5X speedup running Synopsys PrimeSim using NVIDIA B200 GPU-accelerated EC2 instances, demonstrating how GPU infrastructure is penetrating semiconductor design workflows. The performance gain reduces simulation times that traditionally bottleneck chip development cycles.
NVIDIA announced strategic partnerships with Synopsys and Applied Materials at GTC 2026 on March 16, extending GPU acceleration into electronic design automation (EDA) and quantum chemistry workflows.
Synopsys launched AgentEngineer L4, an agentic workflow system that leverages GPU acceleration for chip design tasks. The tool represents a shift from traditional CPU-based EDA software to AI-accelerated design processes, potentially reshaping engineering productivity metrics across the semiconductor industry.
Jitendra Mohan from Astera Labs confirmed that NVIDIA B200 GPU-accelerated computing on AWS has significantly reduced simulation times for their chip design operations. The AWS partnership creates a cloud-accessible infrastructure for GPU-accelerated EDA, lowering barriers to adoption beyond on-premise data centers.
The ecosystem creates a self-reinforcing cycle: AI chip makers use NVIDIA GPUs to design chips faster, which increases demand for GPU infrastructure, which funds further GPU development.
For semiconductor investors, the EDA integration expands NVIDIA's total addressable market beyond inference and training into design tools. Traditional EDA vendors like Synopsys and Cadence face pressure to optimize for NVIDIA architectures or risk performance disadvantages. Chipmakers without access to GPU-accelerated design tools may fall behind on time-to-market metrics, creating competitive moats tied to infrastructure spending rather than design talent alone.
The partnerships announced March 16 suggest NVIDIA is vertically integrating across the chip development stack, from design software through manufacturing simulation to final product deployment. This strategy could lock in customers at multiple touchpoints in the semiconductor lifecycle.
